In digital television broadcasting, a high-frequency receiving device which demodulates a high-frequency signal into I and Q quadrature baseband signals is required in receiving a high-frequency signal (quadrature digital modulation signal) transmitted from a broadcasting station.
FIG. 8 illustrates a general arrangement of a high-frequency receiving device 101 which demodulates a high-frequency signal into I and Q quadrature baseband signals.
In the high-frequency receiving device 101, first, a high-frequency signal transmitted from a broadcasting station is inputted through an input terminal 102 and amplified in a gain variable high-frequency amplifier 103. A frequency of the amplified high-frequency signal is converted in mixer circuits 108 and 109 so as to detect I and Q quadrature baseband signals. The mixer circuit 108 demodulates the high-frequency signal into an I baseband signal by using a 0° signal outputted from a 90° phase shifter 107. Meanwhile, the mixer circuit 109 demodulates the high-frequency signal into a Q baseband signal by using a 90° phase-shifted signal outputted from the 90° phase shifter 107. Each of the two mixer circuits 108 and 109 demodulates the received high-frequency signal into each quadrature baseband signal.
An output of the mixer circuit 108 is amplified in a gain variable baseband amplifier 110. Then, a frequency component out of a desired band is blocked by a low-pass filter 112. Furthermore, an output of the low-pass filter 112 is amplified by an amplifier 114 and outputted as a baseband output (I) from a baseband output terminal 116. Similarly, an output of the mixer circuit 109 is amplified in a gain variable baseband amplifier 111. Then, a frequency component out of a desired band is blocked by a low-pass filter 113. Furthermore, an output of the low-pass filter 113 is amplified by an amplifier 115 and outputted as a baseband output (Q) from a baseband output terminal 117.
A voltage-control local oscillator (VCO) 104, in order to convert a frequency of a high-frequency signal into a frequency of a baseband signal, outputs to the 90° phase shifter 107 a local signal whose frequency is controlled by a control voltage. A local oscillator 105 generates a frequency signal serving as a reference of the local signal.
A PLL circuit 106, based on the frequency signal generated in the local oscillator 105, performs feedback control so that the local signal converges at a value in accordance with a set cycle. The 90° phase shifter 107 generates a 90° phase-shifted signal and outputs the 90° phase-shifted signal and a 0° signal. The 90° phase-shifted signal is a signal whose phase is shifted by 90° from that of the local signal. The 0° phase-shifted signal is a signal whose phase is not shifted at all from that of the local signal.
FIG. 9 illustrates an example arrangement of a general PPL circuit used as the PLL circuit 106. The PLL circuit is for example a circuit disclosed in Document 1: Japanese Laid-Open Publication No. 318732/2003 (Tokukai 2003-318732; published on Nov. 7, 2003: Corresponding U.S. patent Publication 2003/0203720A1; published on Oct. 30, 2003).
The PLL circuit 106 illustrated in FIG. 9 includes frequency dividers 118 and 119, counters 120 and 121, a phase comparator 122, a current source 123, and a low-pass filter (LPF) 124.
An output signal of the local oscillator 105 is divided by the frequency divider 118 at a fixed frequency-dividing ratio. Further, an output signal of the VCO 104 is divided at a fixed frequency-dividing ratio by the frequency divider 119 equivalent to a prescaler. The counters 120 and 121 further divide the frequency-divided signals by counting up (or counting down) the frequency-divided signals. The counter 120 is a functional equivalent of a fixed frequency divider in the PLL circuit of Document 1. Further, since it is possible to divide an output signal of the local oscillator 105 with the counter 120 alone, the frequency divider 119 may be omitted. A cycle (frequency-dividing cycle) of the counter 121 is set by a set cycle inputted from outside. Since the set cycle has a value in accordance with a channel frequency, a frequency of a signal counted by the counter 121 is divided in accordance with the channel frequency.
Note that although a cycle of the counter 20 is also usually set, the process is omitted here. Each of the counters 120 and 121 outputs a signal every time a single cycle is counted. The phase comparator 122 outputs a phase difference between the counters 120 and 121. The current source 123 outputs a predetermined current at a time in accordance with the output (phase difference) of the phase comparator 122. The LPF 124 has a capacitor. The capacitor is charged and discharged by the output current from the current source 123, so that the current is converted into a voltage. The voltage becomes a control signal of the VCO 104. The control signal is used to perform feedback control.
Further, as disclosed in Document 2: Japanese Laid-Open Publication No. 307459/2000 (Tokukai 2000-307459; published on Nov. 2, 2000), the set cycle of the counter 121 is usually inputted through a serial bus (data signal line) into the PLL circuit 106.
In order to receive a high-frequency signal, it is necessary to input a set cycle in accordance with the high-frequency signal into a counter in the PLL circuit 106. However, since the set cycle is usually inputted through a serial bus, there is such a problem that it takes time to set a cycle.
For example, as illustrated in FIG. 10, when a cycle of the 24-bit counter 121 is set by using an I2C bus serving as a typical serial bus, it takes approximately 7 msec (millisecond) under such a condition that the I2C bus is operated at 400 kHz. Moreover, when the number of bits of the counter 121 increases, the setting time is lengthened proportionately.